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LIVE WEBINAR: CDC Verification Flow for OpenCores IP Design

Presenter: Alexander Gnusin, Verification Methodology Specialist Aldec

 Thursday, November 16th, 2017

Time: 3:00 PM – 4:00 PM (CET)
Thursday, November 16th, 2017
Register Now
Time: 11:00 AM – 12:00 PM (PST)
Thursday, November 16th, 2017
Register Now

OpenCores is a well-known open source hardware community for digital open source hardware designs. Many hardware designers have adopted OpenCores IP, hence, it is crucial that they are carefully verified during the IP selection process. One of the verification aspects is the Clock Domain Crossing (CDC) Signoff. In this webinar, we will demonstrate how to apply CDC verification on the OpenCores Ethernet MAC IP.

CDC verification requires design constraints for synthesis and static timing analysis. However, in most cases, OpenCores designs do not include these constraints. In this webinar, we will demonstrate a semi-automatic design constraint generation methodology with ALINT-PRO CDC efficient debugging flow. Using this flow, designers are able to reveal critical CDC issues while generating and verifying timing constraints for the current designs.

  • The Overview of CDC design issues
  • Short Overview or OPenCores Minimac IP
  • MiniMac IP preparation for CDC Analysis
  • Running Default LINT analysis to determine IP quality
  • Design Constraints generation for CDC analysis
  • Running CDC verification and analyzing results
  • ALINT-PRO CDC analysis Live Demo
  • Conclusion
  • Q&A
Alexander Gnusin

Presenter Bio:

Alexander Gnusin is a  Design Verification Technologist with Aldec. He has accumulated 22 years of hands-on experience in various aspects of ASIC and FPGA design verification. His list of employers have included IBM, Nortel and Synopsys Inc.

Take a look at upcoming and previous webinars:

View On Demand Webinars
View Upcoming Webinars

Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

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