Cocotb is a CO-routine based CO-simulation Testbench environment for verifying VHDL/Verilog RTL using Python. It is an open-source environment and hosted on Github.
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LIVE WEBINAR: Effective Testbench Creation Using Cocotb and Python

Presenter: Sunil Sahoo, Applications Engineer Aldec

 Thursday, November 9, 2017

EU TIME ZONE
Time: 3:00 PM – 4:00 PM (CET)
Thursday, November 9th, 2017
Register Now
US TIME ZONE
Time: 11:00 AM – 12:00 PM (PST)
Thursday, November 9th, 2017
Register Now
Abstract:

Cocotb is a CO-routine based CO-simulation Testbench environment for verifying VHDL/Verilog RTL using Python. It is an open-source environment and hosted on Github. It uses the same design-reuse and functional verification concepts like UVM, however is implemented in Python.

In this webinar, we will introduce Cocotb, and will outline how Cocotb can provide significant savings in development time, promote code re-use and ultimately reduce project time-to-market and total development cost.

 
Agenda:
  • Introduction/Slides
  • Live demo
  • Conclusion
  • Q&A
Sunil Sahoo

Presenter Bio:

Sunil Sahoo provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions that include Digital Design Engineer Verification Engineer and  Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.

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Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

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