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UVM for FPGAs (Part 1): Get, Set, Go – Be Productive with UVM

Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks
Thursday, September 9, 2021


The Accelera Universal Verification Methodology (UVM) became an IEEE standard published as IEEE 1800.2 – IEEE Standard for UVM Language Reference Manual (LRM).  UVM has been the predominant verification methodology for ASIC designs for many years and has recently gained popularity and usage with FPGA designs. 

UVM can improve interoperability and reduce the cost of reusing and integrating IPs. Think of lego-like verification process based on pre-built pieces/components/IPs - that’s precisely what UVM provides to design teams. Learning UVM can take a long time especially if one were to go by the extensive information provided in the LRM. In this webinar, we will cover the basics of UVM and how to get more productive with tips, tricks and techniques. We will walk through basic UVM features from a typical end-user perspective and learn to build a small testbench with UVM. 


  • What is UVM?
  • Why UVM?
  • UVM top-down and bottom-up view
  • UVM macros – brief introduction
  • UVM transaction models
  • UVM  Driver
  • UVM Monitor
  • UVM Sequencer  
  • UVM Agent
  • UVM Env
  • UVM Test
  • UVM Sequences
  • Details of Aldec solution
  • Live demo
  • Conclusion
  • Q&A
Event Info                                                                 
EU Session
 3:00 PM – 4:00 PM CEST
 Thursday, September 9, 2021
Register for EU Session
US Session
 11:00 AM – 12:00 PM PDT
 Thursday, September 9, 2021
Register for US Session
Srinivasan Venkataramanan


Srinivasan Venkataramanan, Srini, is a technology entrepreneur with 23+ years of experience in Semiconductors and EDA. Srini has been involved in leading design verification languages and methodologies such as SystemVerilog, UVM, e (Specman), PSL and more since their origin (since early 2000). As part of his latest venture AumzDA he is deploying AI & ML to solve complex design verification challenges. Srini also heads VerifWorks, a high-end design and verification consulting firm. Srini has delivered training on SystemVerilog, UVM, Low Power (UPF), Portable Stimulus and more. He has trained more than 15,000 engineers in live class rooms. His Udemy courses have more than 4000 students to-date. Prior to his entrepreneurial journey, Srini has worked at Intel, Synopsys, Realchip and Philips. 

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Aldec is a pioneer in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Emulation, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, High Performance Computing,  Requirements Management, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

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