LIVE WEBINAR:
Why Should Our Team be Using VHDL + OSVVM for Verification? (EU)
Jim Lewis, VHDL Design and Verification Expert, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, August 15, 2024
4:00 PM - 5:00 PM (CEST)
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Abstract:
This is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team.
Description:
About OSVVM
OSVVM is a suite of libraries designed to streamline your VHDL entire verification process, boosting productivity and reducing development time. Each library provides independent capabilities, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing, OSVVM facilitates writing concise and readable test cases for both unit/RTL tests and complex FPGA and ASIC tests.
Presenter Bio:
Jim Lewis, VHDL Design and Verification Expert, Trainer, OSVVM developer, and IEEE VHDL Chair
Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr. Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.