VHDL-2019: Just the New Stuff (Four Part Webinar Series)
Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment
Part 2: Protected Types Enhancements & Data Structures
Part 3: RTL Enhancements
Part 4: A Testbench Collection of Enhancements
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Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
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Part 2: Protected Types Enhancements & Data Structures
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
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Part 3: RTL Enhancements
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
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Part 4: A Testbench Collection of Enhancements
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
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Bio:
The presenter, Jim Lewis, is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
Whether teaching, developing OSVVM, doing consulting VHDL development, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
