LIVE WEBINAR: Verifying Resets and Reset Domain Crossings (US)

Presenter: Alex Gnusin, Design Verification Technologist

Thursday, March 1, 2018

11:00 AM – 12:00 PM PST

Abstract: 

Correct and clean reset strategy is essential for multi-million gate FPGA and ASIC devices. The possibility to start device operation from a potentially wrong state may cause malfunctions of hardware designs. Also, asynchronous resets may cause metastability effects, causing design malfunction and overheating due to increased power consumption.

This webinar will describe Reset Structures and Reset Domain Crossings verification methodology and rules, demonstrated on demo designs using ALINT-PRO. The methodology behind ALINT-PRO includes careful static reset verification and ensuring valid design functionality (after resets de-assertion and an absence of metastability issues during reset assertion).

Agenda: 

• Resets Verification: The Overview
• Reset types in ASIC and FPGA devices
• Reset Synchronization Techniques
• Reset trees validation in ALINT-PRO
• Constraining Resets
• Reset Domain Crossings: an overview
• Reset Domain Crossings verification in ALINT-PRO
• ALINT-PRO Reset Verification Live demo
• Conclusion
• Q&A

Presenter Bio:

Alexander Gnusin is a  Design Verification Technologist with Aldec. He has accumulated 22 years of hands-on experience in various aspects of ASIC and FPGA design verification.  His list of employers have included IBM, Nortel and Synopsys Inc.