LIVE WEBINAR: UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates (US)
Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks
Thursday, October 7, 2021
11:00 AM – 12:00 PM PT
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Abstract:
Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.
UVM is currently the most adopted industry standard in VLSI/Semiconductor design world. With decades of proven Best Known Methods (BKMs), UVM brings productivity to every team in short span of time. In this webinar, we will walk through UVM evolution over a decade in Accellera and then in IEEE since 2017. Some of the changes are backward incompatible and needs attention from users while migrating.
Agenda:
Presenter Bio:
Srinivasan Venkataramanan, Srini, is a technology entrepreneur with 23+ years of experience in Semiconductors and EDA. Srini has been involved in leading design verification languages and methodologies such as SystemVerilog, UVM, e (Specman), PSL and more since their origin (since early 2000). As part of his latest venture AumzDA he is deploying AI & ML to solve complex design verification challenges. Srini also heads VerifWorks, a high-end design and verification consulting firm. Srini has delivered training on SystemVerilog, UVM, Low Power (UPF), Portable Stimulus and more. He has trained more than 15,000 engineers in live class rooms. His Udemy courses have more than 4000 students to-date. Prior to his entrepreneurial journey, Srini has worked at Intel, Synopsys, Realchip and Philips.