LIVE WEBINAR: UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help (US)

Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks

Thursday, September 23, 2021

11:00 AM – 12:00 PM PT


The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom IPs with memory-mapped registers. While these IPs vary in size and complexity, they are all configurable via registers that are typically composed of a field name, field width, access type, default values and policies. RTL simulations for verifying these IPs especially in various configurations require the use of hierarchical register models - creating them is not a trivial task and require a common framework and automation.

UVM provides a well-defined framework for modeling registers, commonly referred to as the Register Abstraction Layer (RAL). UVM RAL provides APIs to configure registers with various access policies including RW, RO, WO, W1S and RC. It also provides a set of handy pre-built sequences to automate certain common verification scenarios. A robust API on top of register model enables users to develop more automation on top of the built-in features.

In this webinar we will introduce UVM RAL and how the register models can be auto-generated in UVM from a standard IP-XACT format of CSV spreadsheet. We will also show how to use UVM RAL to model Zynq MPSoC registers.


  • Zynq MPSoC design characteristics 
  • UVM RAL introduction
  • Anatomy of UVM Register models
  • Auto-generation of RAL models
  • Adapter modeling in UVM RAL
  • Using RAL to model Zynq MPSoC registers
  • Details of Aldec solution
  • Live demo
  • Conclusion
  • Q&A

Presenter Bio:

Srinivasan Venkataramanan

Srinivasan Venkataramanan, Srini, is a technology entrepreneur with 23+ years of experience in Semiconductors and EDA. Srini has been involved in leading design verification languages and methodologies such as SystemVerilog, UVM, e (Specman), PSL and more since their origin (since early 2000). As part of his latest venture AumzDA he is deploying AI & ML to solve complex design verification challenges. Srini also heads VerifWorks, a high-end design and verification consulting firm. Srini has delivered training on SystemVerilog, UVM, Low Power (UPF), Portable Stimulus and more. He has trained more than 15,000 engineers in live class rooms. His Udemy courses have more than 4000 students to-date. Prior to his entrepreneurial journey, Srini has worked at Intel, Synopsys, Realchip and Philips. 


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