UVM for FPGAs (Four Part Webinar Series)
Part 1: Get, Set, Go – Be Productive with UVM
Part 2: Solving FPGA Verification Challenges with UVM
Part 3: Verifying Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help
Part 4: IEEE 1800.2 UVM Updates
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Part 1: Get, Set, Go – Be Productive with UVM (EU)
Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks
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Part 2: Solving FPGA Verification Challenges with UVM
Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks
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Part 3: Verifying Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help
Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks
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Part 4: IEEE 1800.2 UVM Updates
Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks
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Bio:
Srinivasan Venkataramanan, Srini, is a technology entrepreneur with 23+ years of experience in Semiconductors and EDA. Srini has been involved in leading design verification languages and methodologies such as SystemVerilog, UVM, e (Specman), PSL and more since their origin (since early 2000). As part of his latest venture AumzDA he is deploying AI & ML to solve complex design verification challenges. Srini also heads VerifWorks, a high-end design and verification consulting firm. Srini has delivered training on SystemVerilog, UVM, Low Power (UPF), Portable Stimulus and more. He has trained more than 15,000 engineers in live class rooms. His Udemy courses have more than 4000 students to-date. Prior to his entrepreneurial journey, Srini has worked at Intel, Synopsys, Realchip and Philips.
