Using OVL for Assertion-Based Verification of Verilog and VHDL Designs (EU)

LIVE WEBINAR: Using OVL for Assertion-Based Verification of Verilog and VHDL Designs (EU)

Alexander Gnusin, Design Verification Technologist

Thursday, October 21, 2021

3:00 PM - 4:00 PM (CET)

Abstract:

Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement assertion-based verification of their design. Finally, OVL supports any HDL language (Verilog, SystemVerilog, VHDL), enabling assertion-based verification with any simulation tools.

In this webinar, we will present practical guidance on how to start using Open Verification Library (OVL) in design and verification process. We will provide various code examples to demonstrate how to efficiently use OVL for Verilog and VHDL design verification. Static formal and emulation-based verification methods using OVL will be outlined as well.

Agenda:

Assertion-Based Verification: An Overview
Introduction to Assertion-Based Verification with OVL
Applying OVL – based verification on HDL designs
Using OVL checkers in emulation/prototyping
Formal Model checking with OVL
Live demo
Conclusion
Q&A

Presenter Bio:

Alexander Gnusin

Alexander Gnusin, Design Verification Technologist. Alex accumulated 25 years of hands-on experience in various aspects of ASIC and FPGA design and verification. His employees list includes IBM, Nortel, Ericsson and Synopsys Inc. As Verification Prime for a multi-million gates project, he combined various verification methods - LINT, Formal Property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.