LIVE WEBINAR: Using ALINT-PRO to Verify Clock Domain Crossing Issues in FPGA designs (US)

Presenter: Alexander Gnusin, Design Verification Technologist

Thursday, December 12, 2019

11:00 AM – 12:00 PM PST

Abstract: 

The Clock Domain Crossing Issues cause functional instability of FPGA designs. It is extremely hard to understand the cause of such issues. Even though design is working perfectly in Functional simulations, it may still fail during Lab Testing. Recently, FPGA vendors (such as Xilinx) introduced certain amount of CDC checks into their development environments. However, these checks are not sufficient and has to be enhanced with the third-party CDC verification tools.

ALINT-PRO provides smooth and practical solution for the FPGA Projects Code Linting and enhanced Clock Domain Crossings Verification. The automated code conversion allows FPGA designers to load complex FPGA projects into the ALINT-PRO environment in seconds. The enhanced Clock Domain Crossing Verification with ALINT-PRO is able to reveal hard-to find issues causing functional instability of FPGA designs. Current webinar explains this methodology and demonstrates it on the real-world FPGA design.

Agenda: 

• CDC Issues Overview
• CDC Verification with FPGA Vendors tools:
• Xilinx Vivado CDC checks
• Intel FPGA Quartus CDC checks
• Enhanced CDC Verification Flow with ALINT-PRO:
  • Running CDC Verification with FPGA Vendor tools
  • Converting FPGA projects to ALINT-PRO
  • Enhanced CDC Verification with ALINT-PRO
• Demo
• Summary
• Q&A

Presenter Bio:

Alexander Gnusin accumulated 24 years of hands-on experience in various aspects of ASIC and FPGA design verification. His employees list includes IBM, Nortel and Synopsys Inc.