LIVE WEBINAR:
Turbocharge your FPGA Simulation Workflows:
Part 3 - High-Performance RTL Simulation Workflow with Libero and Active-HDL(US)
Louie De Luna, Director of Marketing at Aldec
Thursday, April 4, 2024
11:00 AM - 12:00 PM (PST)
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Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs). Major FPGA vendors like AMD, Altera and Microchip are continuously innovating their technologies, architectures, and IPs – and consequently enhancing their respective design capabilities and workflows. For example, Vivado, Quartus and Libero all provide useful design and RTL simulation features. Aldec collaborates closely with the FPGA vendors as partners to ensure seamless simulation of all their IPs and libraries using Aldec’s simulation tool, Active-HDL.
In terms of verification, FPGA designs undergo testing directly in the lab or through simulations, depending on factors such as design size, complexity, and project objectives. While some FPGA designs may find adequate simulation support from the FPGA vendor tools, many require higher simulation performance and a more comprehensive language support, particularly those with larger designs with complex logic and deep hierarchies.
Simulation stands as the primary verification method for FPGA designs, essential for minimizing non-trivial bugs escaping into production. The ability to run more simulation enables the verification of a wider range of test scenarios, thus elevating verification quality. Aldec’s Active-HDL offers a faster compilation/simulation engine, robust debugging features and comprehensive language support for the latest versions of VHDL, SystemVerilog, and SystemC.
In this three-part webinar series, we will show how to turbocharge FPGA simulation workflows by using Active-HDL as the default simulator within AMD® Vivado, Altera® Quartus and Microchip® Libero SoC.
Abstract:
In the concluding part of this three-part webinar series, we will show how to simulate a Microchip design example. We will generate a design example from Libero SoC and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and, depending on your budget/resource constraints, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench and we will perform debugging using Breakpoints, Xtrace, Drivers/Readers and Advanced Dataflow.
- Workflow with Libero SoC and Active-HDL
- Tips on how to optimize simulation performance
- Performance bottleneck analysis with Design Profiler
- Breakpoints, Xtrace and Advanced Dataflow, Drivers and Readers
- Live Demo
- Q&A
- 45 min presentation/live demo
- 15 min Q&A
Presenter Bio:
Louie De Luna, Director of Marketing at Aldec
Louie De Luna is Aldec’s Director of Marketing with 20+ years’ experience in FPGA/SoC design verification and EDA tools. He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada, Las Vegas, in 2001. His practical engineering experience includes simulation-based verification, linting, CDC analysis, and hardware-assisted verification.
