LIVE WEBINAR: The most error prone FPGA corner cases (EU)

Presenter: Espen Tallaksen, CEO of EmLogic

Thursday, October 14, 2021

3:00 PM – 4:00 PM CEST

Abstract:

Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. 

To explain this in a simple way, - a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals. Then a typical cycle related corner case is if you read/reset the counter in the same cycle as a new event occurs – risking strange behaviour in many ways. For this simple example however, most designers will handle this correctly, - but for more complex examples – including something as simple as a UART, this type of corner case is extremely error prone.

This webinar will explain these corner cases in more detail and then show why they often result in bugs, why these bugs are often not detected, and how you can detect them.

Agenda: 

• What is a cycle related corner case?
• Why is this problem?
• What does a typical error prone code look like?
• What is the probability of detecting or testing such a corner case?
• Why are the common solutions not working?
• Independent of tools, what is required to detect these corner cases?
• How can you use UVVM to detect these corner cases?
• Conclusion
• Q&A

Presenter Bio:

Espen Tallaksen, Founder and CTO of Bitvis.

Espen is also the author and architect of UVVM and founder of previous Bitvis. 

He has a strong interest for methodology cultivation and pragmatic efficiency and quality improvement, and he has given many presentations on various international conferences with great feedback. He has also given courses on FPGA Design and Verification on three different continents.