LIVE WEBINAR: Static Verification for RISC-V Cores and SoCs (EU)

Presenter: Alexander Gnusin, Design Verification Technologist

Thursday, October 1, 2020

3:00 PM – 4:00 PM CEST

Abstract: 

The entire processor industry is currently going through a paradigm shift - new generations of domain-specific proprietary processor cores based on the open-source RISC-V ISA are now being developed by various industry-leading semiconductor companies. Additionally, open-source RISC-V processor cores such as SweRV, Ibex and Pulp are now available, and they are actively being developed in various open-source Github communities. 

Static verification or linting is a standard part of the tool flow for any processor-based designs to help engineers develop highly robust code in both IP and SoC levels. Static linting based on industry-best practice coding standards are critical in ensuring best-practice coding styles, efficient synthesis and timing closure, avoid simulation-to-synthesis mismatches, and proper usage of SystemVerilog constructs and data types. In this presentation, we will demonstrate how to statically verify RISC-V IP designs with the new ALINT-PRO RISC-V ruleset.

Agenda: 

• Current RISC-V design verification flow : the Overview
• Advanced Linting with ALINT-PRO RISC-V Rules Plugin
  • ALINT-PRO Lintong for IP designs
  •  RISC-V Plugin overview
• Running Advanced Linting on RISC-V designs:
  • Live demo of RISC-V cores linting
  • Issues & violations Analysis
• Summary
• Q&A

Presenter Bio:

Alex accumulated 25 years of hands-on experience in various aspects of ASIC and FPGA design and verification. His employees list includes IBM, Nortel, Ericsson and Synopsys Inc. As Verification Prime for a multi-million gates project, he combined various verification methods - LINT, Formal Property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.