Static and Dynamic CDC Verification of AXI4 Stream-based IPs (US)

LIVE WEBINAR SERIES:

Static and Dynamic CDC Verification of AXI4 Stream-based IPs (US)

Alex Gnusin, Aldec’s ALINT-PRO Product Manager

Thursday, October 17, 2024

11:00 AM - 12:00 PM (PST)

Abstract:

The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP, capable of changing clock domains when packet routing is not required.

Static and dynamic clock domain crossing (CDC) verification methods complement each other to ensure flawless operation of multi-clock designs. ALDEC_CDC rules plugin contains 58 rules for checking design quality, design constraints, and clock and reset trees. It is also used for validating design synchronization circuits. However, static CDC verification methods alone may not guarantee the completeness of the CDC verification task. Dynamic CDC verification is crucial. The two main methods for dynamic CDC verification are checking with CDC assertions and modeling of random delay insertion on clock domain crossings.

In this webinar, we will introduce both static and dynamic verification methods for CDC verification of AXI4 Stream-based IPs. We will discuss the CDC assertions that are auto-generated from ALINT-PRO, and we will also demonstrate the design and usage of the synchronizer models with random delay insertion.

Agenda:

CDC verification process overview
- Static CDC verification checks
- Assertions usage in CDC verification
- The concept of delay randomization at CDC crossing in functional simulation
AXI Stream protocol overview
AXI CDC Port Verification
- Running CDC static checks with ALINT-PRO
- Generation SV Assertion with ALINT-PRO
- Developing the testbench for AXI CDC Port dynamic verification
- Simulating design with generated CDC assertions
- Simulating design with random delay insertion in synchronizer models
Conclusion
Q&A

Webinar Duration

45 min presentation/live demo
15 min Q&A

Presenter Bio:

Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification.

Alex Gnusin, Aldec’s ALINT-PRO Product Manager

Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.