LIVE WEBINAR SERIES:
Static and Dynamic CDC Verification of AXI4 Stream-based IPs (EU)
Alex Gnusin, Aldec’s ALINT-PRO Product Manager
Thursday, October 17, 2024
4:00 PM - 5:00 PM (CET)
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Abstract:
The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP, capable of changing clock domains when packet routing is not required.
Presenter Bio:
Alex Gnusin, Aldec’s ALINT-PRO Product Manager
Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.