LIVE WEBINAR: Shortening verification time of safety critical projects (EU)

Presenter: Janusz Kitel, DO-254 Program Manager at Aldec

Thursday, February 27, 2020

3:00 PM – 4:00 PM CET

Abstract: 

For today’s designs the verification process may take much more time than the design phase. It happens especially for safety critical designs where extra objectives related to traceability, test in real hardware or robustness testing must be achieved. The solution is not only to make the simulation run faster but also to satisfy the safety critical objectives without extra workload.

During this presentation we will show how you can speed up your verification phase and satisfy the verification objectives of DO-254 at a very short time by using our DO-254/CTS™ hardware verification platform.

Agenda:

• Hardware testing with simulation testbench reuse
• Regression testing on real hardware
• Waveform analysis from physical testing
• Robustness testing
• Satisfying DO-254 objectives for verification

Presenter Bio:

Janusz Kitel is a DO-254 Program Manager at Aldec. He is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. Janusz has 7 years of experience in requirements engineering and over 12 years of experience in product quality assurance. Janusz received his M.S. in Electronics and Telecommunication from Silesian University of Technology and increased his knowledge around software engineering from complementary studies at AGH University of Science and Technology (Poland). His practical engineering experience includes the areas of functional verification, DO-254 compliance and software development and he has held a wide range of engineering positions that include Application Engineer, Software Developer and Project Manager.