The RISC-V ISA has opened tremendous opportunities creating a breeze of fresh air in the ARM dominated design houses of embedded SoC projects. We didn’t have to wait long until the first RTL implementations of the RISC-V processor were started (both open source and commercial). Currently there are several open source projects of RISC-V CPU cores. There is however a verification gap between the open source fabless design and the ones that are intended to be taped out. The HDL/RTL simulation that works well for research and open source projects is not sufficient in case of huge investments in chip fabrication where designs must be verified exhaustively.
In this webinar we will present how FPGA hardware-assisted verification such as simulation acceleration, emulation and prototyping can be used at different verification stages to bridge the verification gap, increase functional test coverage and enable true hardware-software co-verification of RISC-V cores and SoCs.
- RISC-V System-on-Chip Verification Challenges
- Verification With Hardware In The Loop - Stages & Methods
- Introduction to Aldec HES-DVM Hardware Assisted Verification
- RISC-Verification Cases:
- Simulation Acceleration
- Hybrid Co-Emulation
- Physical Prototyping