LIVE WEBINAR SERIES:
Practical LLM Techniques for FPGA Functional Verification (US)
Alex Gnusin, Aldec’s ALINT-PRO Product Manager
Thursday, October 29, 2026
11:00 AM - 12:00 PM (PDT)
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Abstract:
Frontier large language models (LLMs) from companies such as Anthropic and OpenAI continue to improve at a remarkable pace, expanding the range and complexity of engineering tasks with which they can reliably assist. For FPGA verification engineers, LLMs can automate repetitive tasks, accelerate testbench development, and improve productivity throughout the design verification flow.
This webinar presents practical techniques and best practices for using general-purpose LLMs to support FPGA functional verification. Through real-world examples and live demonstrations, you'll learn how LLMs can assist with creating verification plans from design specifications, generating SystemVerilog and VHDL testbench components, writing assertions, creating functional coverage models, and generating test sequences.
The session will also cover techniques for validating LLM-generated content, common pitfalls to avoid, and the current strengths and limitations of LLMs. Rather than introducing a proprietary verification solution, the focus is on helping verification engineers use today's widely available LLM tools more effectively in their existing verification workflows.
Whether you're new to LLMs or already incorporating them into your daily workflow, you'll leave with practical techniques that can be immediately applied to improve productivity, accelerate verification, and enhance the quality of FPGA functional verification.
- Introduction
- What are Large Language Models (LLMs)?
- The rapid evolution of frontier LLMs
- Why LLMs matter for FPGA functional verification
- Opportunities and current limitations
- Applying LLMs Throughout the Verification Flow
- Creating verification plans from design specifications
- Generating SystemVerilog and VHDL testbench components
- Writing assertions
- Creating functional coverage models
- Generating test sequences
- Best Practices
- Validating LLM-generated code and documentation
- Common pitfalls and limitations
- Integrating LLMs into existing verification workflows
- Live Demonstrations with Riviera-PRO
- Conclusion
- Q&A
Presenter Bio:
Alexander Gnusin
Aldec’s ALINT-PRO Product Manager
Alex has almost 30 years of hands-on experience in various aspects of ASIC and FPGA design and verification. In a previous role and as Verification Prime on a multi-million gates project, Alex combined various verification methods including static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. Alex has an M.S. in Electronics, awarded from Technion, Israel Institute of Technology, and his former employers include IBM, Nortel, Ericsson and Synopsys.
