Practical Co-Simulation Techniques with OSVVM Part 2: RISC-V Software and Logic Co-Development (US)

LIVE WEBINAR SERIES:

Practical Co-Simulation Techniques with OSVVM

Part 2: RISC-V Software and Logic Co-Development (US)

Simon Southwell, Freelance Logic and Software Consultant,

specializing in co-simulation, HPC and wireless solutions

Thursday, September 3, 2026

11:00 AM - 12:00 PM (PST)

Abstract:

OSVVM is a powerful open-source VHDL verification methodology and library widely adopted for FPGA and SoC verification. It provides a comprehensive set of capabilities including transaction-based verification, constrained randomization, functional coverage, scoreboards, memory models, reusable testbench architectures, and advanced scripting support across leading simulators such as Aldec’s Active-HDL and Riviera-PRO.

As embedded software and FPGA logic become increasingly interconnected, verification teams require efficient ways to validate hardware and software together within a unified simulation environment.

In this, the second webinar in our three-part series, we explore how OSVVM co-simulation enables RISC-V software and logic co-development using C/C++ instruction set simulators (ISS). The session demonstrates how software workloads can interact directly with FPGA-based logic simulations to accelerate system-level verification and embedded software validation.

Attendees will learn how to integrate the OSVVM rv32 RISC-V ISS model into an OSVVM verification environment, develop software-driven test scenarios, and build scalable verification flows for embedded applications. The session also includes a live demonstration of co-simulating a RISC-V program using the rv32 ISS within an OSVVM test environment. In addition, the webinar explores future directions for RISC-V support and co-simulation capabilities within the OSVVM ecosystem.

Webinar Agenda:

Overview of OSVVM Co-Simulation
Hardware/Software Co-Development Challenges
Running a RISC-V Instruction Set Simulator in OSVVM
Introduction to the rv32 RISC-V ISS Model
Integrating the ISS into an OSVVM Testbench
Creating Software-Driven Verification Scenarios
Debugging and Analyzing Co-Simulation Results
Demonstration: Co-simulation of a RISC-V program using the rv32 ISS within an OSVVM test environment
Future RISC-V Enhancements in OSVVM
Q&A

Webinar Duration:

45 min presentation/live demo
15 min Q&A

Presenter Bio:

Simon Southwell, Freelance Logic and Software Consultant

Simon Southwell,

Freelance Logic and Software Consultant

Simon Southwell, Freelance Logic and Software Consultant, specializing in co-simulation, HPC and wireless solutions. Engineer with 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development. Now spending time contributing IP to the open-source community, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also currently a collaborator on the OSVVM project, a verification methodology and VHDL library, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems, system modelling in software, the software/hardware interface and co-simulation of logic and software.

Amongst the many areas of experiences are original logic IP design targeting both ASIC and FPGA, logic verification, HPC (supercomputers), processor systems, networking (802.3 and proprietary), embedded software, co-simulation technology, software modelling of SoC systems, data compression logic, PCIe endpoint design, cellular (3G and 4G), wireless (802.11 and 802.15.4) and more. Joint or sole author on several logic IP related patents.