OSVVM: The New Stuff (EU)

LIVE WEBINAR

OSVVM: The New Stuff (EU)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, & IEEE VHDL Chair

Thursday, September 2, 2021

3:00 PM – 4:00 PM CEST

Abstract:

During 2020, OSVVM had 6 updates. 2021 continues this pace with a release in February, June, and July. This presentation talks about what is new.

Here is what has changed:

Restructured OSVVM Release Directories (2020.07)

The OSVVM utility library and verification components are now all organized under OsvvmLibraries
This facilitates installing the entire library.

Scripting (2020.07)

Simulator Independent Scripting. One script to run them all.
Layered on top of TCL – so it runs natively in simulators.
2020.07: Refactored tool execution for simplified vendor customizations

Specification and Test Tracking (2020.05, 2020.08)

Uses AlertLogPkg to track requirements or test completions

Model Independent Transactions (2020.07, 2020.10, 2020.12, 2021.06)

Establishes a pattern of transactions for Address Bus and Streaming Interfaces.
2020.02: Created initial Address Bus Interface by refactoring from Axi4Lite.
2020.07: Refactored tool execution for simplified vendor customizations
2020.07: Created Byte based bursting for Address Bus Interfaces
2020.10: Create Byte, Word, and Word+Parameter bursting for streaming interfaces
2020.12: Added Word bursting for Address Bus Interfaces
2021.06: Moved burst FIFOs to internal to Address Bus and Streaming Interfaces

Virtual Transaction Interfaces (2020.12)

2020.12: Added Virtual Transaction Interfaces to AXI4 and AxiStream Verification Components.

AXI4 Full Verification Components (2020.07, 2020.12)

2020.07: Axi4Master (with byte-based bursting), Axi4Memory, Axi4Responder.
2020.12: Added Full Signaling to all.
2020.12: Added word-based bursting to Axi4Master.

AxiStream (2020.07, 2020.10)

2020.07: Updated AxiStreamTransmitter and AxiStreamReceiver to use Stream Model Independent Transactions
2020.10: Added Bursting with Byte, Word, and Word+User bursting.
2020.10: Added documentation for AxiStream Verification components

UART (2020.07)

2020.07: Updated UartTransmitter and UartReceiver to use Stream Model Independent Transactions

Documentation (2020.07, 2020.10, 2020.12, 2021.06)

201X.XX: User guides and/or quick reference cards for all packages in the OSVVM Utility library (aka OSVVM library).
2020.07: User guide for Address Bus Model Independent Transactions (Used by Axi4 full and Axi4Lite).
2020.07: User guide for Stream Model Independent Transactions (used by AxiStream and UART).
2020.10: User guide for AxiStream
2020.12: User Guide for Axi4 Full and Axi4 Full VPI verification components

This webinar provides a guided walk-through of the updates.

Benefits of OSVVM

OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM – or alternately 36% of the VHDL FPGA market uses OSVVM. In Europe, in the FPGA market, OSVVM (with 36%) leads SystemVerilog+UVM (with 26%).

OSVVM is an innovator and leader in the development of VHDL Verification Methodology. Our approach has been evolving in SynthWorks classes since 1997 and started being released as open source in 2011. So how does it compare to SystemVerilog?

Constrained Random – Supported via RandomPkg and coding styles – an OSVVM innovation
Functional Coverage – Supported via CoveragePkg – an OSVVM innovation
Scoreboards – Supported via ScoreboardGenericPkg – an OSVVM innovation
Error reporting and Messaging – supported via AlertLogPkg – concepts borrowed from numerous sources
Transaction based testbenches and verification components – in our classes since 1997
Memory Modeling – data structure for efficient creation of memories through sparse allocation.
Process Synchronization – barrier synchronization (an OSVVM innovation) as well as other methods.

Is OSVVM supported by my simulator? Currently OSVVM is supported by simulators from Mentor, Aldec, Cadence, Synopsys, and GHDL. This is great support and our goal is to keep it this way. When we upgrade existing features in the library, we test to make sure we do not break support within our community. OTOH, when we introduce new capability (generally in separate packages) and there is a significant advantage to using advanced VHDL constructs – such as it simplifies how the item is used, then it is likely we will use it – as a result, some of OSVVM's Verification IP uses records with unconstrained arrays. We also strictly avoid using deprecated language features - such as shared variables that have an ordinary type.

Presenter BIO

The presenter, Jim Lewis, is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.

Whether teaching, developing OSVVM, doing consulting VHDL development, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.

Agenda:

50 min presentation/live demo
10 min Q&A

Presenter Bio:

Jim Lewis

Jim Lewis, is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.