Modeling AMD Zynq MPSoC PS8 Interfaces with OSVVM (EU)

LIVE WEBINAR SERIES:

Modeling AMD® Zynq MPSoC™ PS8 Interfaces with OSVVM (EU)

Adrian Weiland, Embedded Systems Engineer at PLC2 Design GmbH

Thursday, November 12, 2026

4:00 PM - 5:00 PM (CEST)

Abstract:

Vivado Block Designs based on the AMD Zynq UltraScale+ MPSoC can be difficult to verify at the system level when the Processing System (PS) must initiate and respond to AXI transactions, provide memory access, and interact with programmable logic peripherals. This webinar presents a VHDL/OSVVM approach that replaces the PS8 instance during simulation with a behavioral interface model while preserving the original PS8 ports and the synthesizable design structure.

The replacement model uses OSVVM AXI4 and UART Verification Components together with Virtual Transaction Interfaces (VTIs). VHDL configurations bind the simulation model in place of the PS8, while VTI and VHDL external names allow the test controller to access verification components embedded inside the Vivado-generated Block Design hierarchy. The PS8 replacement provides clock and UART behavior, AXI managers for PS-to-PL transactions, and AXI memory models for PL-to-PS accesses.

Using the open-source BigDesign reference design, this webinar demonstrates the resulting OSVVM testbench architecture in Riviera-PRO, including AXI-controlled peripherals, UART testing, memory traffic, and direct access to the simulated memory for verification. This webinar also presents Riviera-PRO performance improvements for simulating large OSVVM memory models. This approach enables the surrounding Vivado Block Design and PL logic to be exercised without modeling the internal processor subsystem, providing a practical VHDL-native verification flow for OSVVM users.

Webinar Agenda:

Why model the PS8 Interfaces for Simulation?
Reference Design and Vivado Block Design Architecture
OSVVM AXI4, UART, and Virtual Transaction Interfaces
Building the PS8 Behavioral Interface Model
Replacing the PS8 for Simulation with VHDL Configurations
Driving Embedded Verification Components with VTI
Simulation using Riviera-PRO
Summary and Outlook
Q&A

Key Takeaways:

Verification of MPSoC Block Designs without requiring the actual PS8 model
Efficient simulation of memory systems significantly larger than 4 GB
Usage of 64-bit addressing and coverage models with OSVVM

Webinar Duration:

45 min presentation
15 min Q&A

Presenter Bio:

Adrian Weiland, Embedded Systems Engineer at PLC2 Design GmbH

Adrian Weiland

Embedded Systems Engineer at PLC2 Design GmbH

Adrian Weiland is an Embedded Systems Engineer at PLC2 Design GmbH with a strong focus on FPGA-based system design and VHDL development. His expertise lies in digital hardware design, verification, and the implementation of high-performance, hardware-accelerated solutions for demanding applications. He actively contributes to open-source VHDL projects, including the PoC Library. He holds a Bachelor’s degree in Embedded Systems Engineering from the University of Freiburg. His current work includes the development and verification of AMD MPSoC-based systems, with a particular focus on simulation, AXI-based architectures, and OSVVM-based verification methodologies.