Making a Structured VHDL Testbench – A Demo for Beginners (EU)

Espen Tallaksen, CEO of EmLogic 

Thursday, April 11, 2024

3:00 PM - 4:00 PM (CET)


This demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches.

This session will show you what is needed for any good testbench, irrespective of its complexity.  
We will make a testbench from scratch for a simple VHDL module and do the following:
  • Add a balanced and controllable clock generator
  • Add logging of progress in a simple way
  • Check default values and reset 
  • Access module via an interface – using BFMs (Bus Functional models)
  • Check output signals with and without a positive acknowledge
  • Wait for flag or interrupt or a given value – with a timeout 
  • Check that signals have been stable – without pulses or spikes for a given time 
  • Report an alert summary
  • … and more
…all  using well-documented VHDL procedures and functions from UVVM, the open source fastest growing VHDL verification methodology.
The presented solution will use UVVM Utility Library and BFMs, but the principles and mechanisms are 100% general verification methodology; i.e., independent of library and available functionality.
Although this testbench is applied on a very simple design under test (DUT), the same principles also apply to advanced testbenches for complex DUTs. (But the advanced testbenches need more on top.)
  • Quality and Efficiency Enablers
  • The simple DUT and simple TB architecture
  • UVVM: Concepts, Download and Compile
  • Making the testbench – prior to test cases
  • Adding clock generator and starting logging and checking
  • BFMs: Explained, Usage, Making simple overloads
  • Alert handling, Verbosity control and Timeouts
  • Conclusion
  • Q&A
Webinar Duration
  • 45 min presentation/live demo
  • 15 min Q&A


Presenter Bio:

Espen is also the author and architect of UVVM and founder of previous Bitvis.

Espen Tallaksen, CEO of EmLogic 

Espen is also the author and architect of UVVM and founder of previous Bitvis. He has a strong interest for methodology cultivation and pragmatic efficiency and quality improvement, and he has given many presentations on various international conferences with great feedback. He has also given courses on FPGA Design and Verification world-wide


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