Introduction to Logic Simulator Programming Interfaces for FPGA Designs                                (Three Part Webinar Series)

Part 1: The Power of Verilog's PLI & VPI (EU)

Presenter: Simon Southwell

Thursday, April 13, 2023

3:00 PM - 4:00 PM (CEST)


The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development.

The Programming Language Interface (PLI/VPI) is part of the IEEE Standard for SystemVerilog Language Reference Manual. In this part 1 of the webinar series, we will introduce the Verilog PLI and VPI and discuss the first steps of crossing from the logic domain to the software domain. We will show various working examples with memory models and virtual processors, sufficient to allow engineers to start creating their own solutions. The real-world examples will be demonstrated to show just what is possible with using these basic logic interface features that are already available, and well supported, in the Aldec simulation tools.
  • Introduction 
  • Verilog PLI
  • Sparse memory model example
  • Verilog VPI
  • Reworked memory model
  • Virtual Processor
  • Demo of Virtual Processor and memory model
  • Conclusions
  • Q&A
Webinar Duration
  • 45 min presentation/live demo
  • 15 min Q&A

Presenter Bio:

Simon Southwell has 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development.

Simon Southwell has 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development. Now spending time contributing IP to the open-source community, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also currently a collaborator on the OSVVM project, a verification methodology and VHDL library, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems, system modelling in software, the software/hardware interface and co-simulation of logic and software.

Amongst the many areas of experiences are original logic IP design targeting both ASIC and FPGA, logic verification, HPC (supercomputers), processor systems, networking (802.3 and proprietary), embedded software, co-simulation technology, software modelling of SoC systems, data compression logic, PCIe endpoint design, cellular (3G and 4G), wireless (802.11 and 802.15.4) and more. Joint or sole author on several logic IP related patents.

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