Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A recently added feature to Aldec’s ALINT-PRO allows designers to extract, review and verify the correctness of bus interface connections. In addition, ALINT-PRO is capable of automatically connecting bus protocol checkers and can monitor the current design to enable functional interconnect verification in simulation.
This webinar presents the bus interfaces extraction technology within ALINT-PRO. The concept of bus interface/interconnect instances will also be discussed. In addition, bus interfaces/interconnects visualization will be demonstrated with the new Interconnect Viewer and the enhanced Elaboration Viewer within ALINT-PRO. The automated process of “non-intrusive” protocol checkers and monitors attachment to design will be presented too.
- An overview of bus interfaces and their types
- Introduction to bus interconnects
- Visualization of bus interfaces in ALINT-PRO
- Static verification of bus interconnects with ALINT-PRO
- Dynamic bus interconnects verification using auto-connected protocol checkers
- Live demo
- 45 min presentation and demo
- 15 min Q&A