The Clock Domain Crossing Verification is one of the most important tasks for ASIC and FPGA design with multiple clock domains. However, there is a need to properly prepare designs for the CDC run.
Most designs include the third-party IP cores, with either protected or unprotected source code. For the Clock Domain Crossing verification, it is highly important to verify the IP-based designs even though the IP contents are protected. To do so, there is a need to develop the CDC model for the protected IP core.
Another problem is the CDC verification of large System-on-the-Chip designs. Due to large design size, it may be impractical to verify all the system at once. Alternatively, it make sense to use the "divide and conquer" approach, running the Clock Domain Crossing verification on leaf design modules, one by one. In order to run the CDC at system level, already verified leaf design modules has to be abstracted to the CDC models and used in the top-level run.
The following webinar will show how to develop CDC models for the protected IP designs and how to run the Clock Domain Crossing verification for large designs, abstracting design block with the CDC models.
- CDC Issues Overview
- CDC Verification Issues for large & IP-based designs
- Blocks Blackboxing concept in ALINT-PRO
- Black box designs Timing characterization for CDC Analysis
- Hierarchical CDC methodology for IP-based designs
- Hierarchical CDC methodology for large designs