LIVE WEBINAR: Functional Verification of Clock Domain Crossing Issues (US)

Presenter: Alexander Gnusin, Design Verification Technologist

Thursday, February 18, 2021

11:00 AM – 12:00 PM PT

Abstract: 

ALINT-PRO provides powerful means for static analysis and validation of clock domain crossings(CDC). It extracts and validates clock trees, and clock domains, applying topological pattern-matching methods to validate the correctness of design structures on the clock domain boundaries. However, static CDC verification has to be augmented with the dynamic CDC verification to ensure the absence of CDC-related issues. For this purpose, ALINT-PRO provides assertion-generation engines, allowing designers to enhance their functional verification with CDC checking code.

The webinar presents the complete clock domain crossing verification methodology, from static verification with ALINT-PRO up to dynamic verification with Riviera-PRO. It includes a number of design examples, for different synchronizer types. Also, the webinar includes a short introduction to Assertion-Based Verification using SystemVerilog Assertions (SVA).

Agenda: 

• Clock domain crossing (CDC) verification methodology
• Static CDC verification
• Dynamic CDC verification
• Assertion-based verification with SVA
• Design examples
• Summary
• Q&A

Presenter Bio:

Alexander Gnusin, Design Verification Technologist. Alex accumulated 25 years of hands-on experience in various aspects of ASIC and FPGA design and verification. His employees list includes IBM, Nortel, Ericsson and Synopsys Inc. As Verification Prime for a multi-million gates project, he combined various verification methods - LINT, Formal Property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.