LIVE WEBINAR: From Traceability to Reusability for Safety-Critical FPGA Projects (EU)

Presenter: Janusz Kitel, Requirements Management Specialist

Thursday, September 13, 2018

3:00 PM – 4:00 PM CEST

Abstract: 

Effective design reuse strategies are expensive and unfortunately will frequently lose when subjected to time and market pressure. However, Engineers frequently find value in reusing code from other projects. The problem is that the knowledge about the legacy code may not be enough to properly assess the worthiness of reusing it.

One possible method to implement reusability is traceability. With traceability, relations and dependencies between requirements, design, test scenarios and verification goals are identified and linked. In this presentation, we propose to enable traceability analysis in the hardware development process in order to achieve reusable requirements, design and verification artifacts.

Agenda: 

• Reusability or recycling
• Factors affecting code reuse.
• Traceability analysis for dealing with legacy code
• Utilizing and sharing the knowledge
• Spec-TRACER™ demo
• Conclusion
• Q&A

Presenter Bio:

Janusz Kitel is a Requirements Management Specialist at Aldec. He is responsible for the Spec-TRACER product line. Janusz has 5 years of experience in requirements engineering and over 10 years of experience in product quality assurance. Janusz received his M.S. in Electronics and Telecommunication from Silesian University of Technology and increased his knowledge about software engineering from complementary studies at AGH University of Science and Technology (Poland). His practical engineering experience includes areas in functional verification, DO-254 compliance and software development.