For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously.
- Testbenches with basic architecture and their limitations
- Components of an efficient and advanced testbench architecture
- VHDL Verification Components (VVC)
- Controlling and checking many interfaces simultaneously
- UVVM, VVC Framework Testbench Sequencer
- 45 min presentation/live demo
- 15 min Q&A