LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency
Part 2: FPGA Verification Architecture Optimization with UVVM (EU)
Espen Tallaksen, CEO of EmLogic
Thursday, May 5, 2022
3:00 PM - 4:00 PM (CEST)
|
Abstract:
For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously.
Agenda:
- Testbenches with basic architecture and their limitations
- Components of an efficient and advanced testbench architecture
- VHDL Verification Components (VVC)
- Controlling and checking many interfaces simultaneously
- UVVM, VVC Framework Testbench Sequencer
- Conclusion
- Q&A
Webinar Duration:
- 45 min presentation/live demo
- 15 min Q&A
Presenter Bio:
Espen Tallaksen, CEO of EmLogic
Espen is also the author and architect of UVVM and founder of previous Bitvis.
He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.
