FPGA Design/Verification Best-Practices for Quality and Efficiency PART 1: FPGA Design Architecture Optimization (EU)

LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency

Part 1: FPGA Design Architecture Optimization(EU)

Espen Tallaksen, CEO of EmLogic

Thursday, April 28, 2022

3:00 PM - 4:00 PM (CEST)

Abstract:

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to increase both quality and efficiency.

The FPGA design architecture also affects several project and product characteristics such as reusability, power consumption, resource usage, timing closure, clocking issues, implementation clarity, review easiness and verification/test workload.

Agenda:

State of the FPGA community
Examples of bad FPGA design architectures (results and disadvantages)
How to improve and optimize FPGA design architectures (results and advantages)
How design and design changes can be simplified
Conclusion
Questions and Answers

Webinar Duration:

45 min presentation/live demo
15 min Q&A

Presenter Bio:

Espen Tallaksen, CEO of EmLogic

Espen Tallaksen, CEO of EmLogic
Espen is also the author and architect of UVVM and founder of previous Bitvis.
He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.