LIVE WEBINAR: Extending IBM® Rational® DOORS® Traceability for FPGA Designs (EU)

Presenter: Janusz Kitel, Requirements Management Specialist

Thursday, February 22, 2018

3:00 PM – 4:00 PM CET

Abstract: 

User requirements, use cases, system level requirements and board level requirements are typically managed in DOORS, but FPGA requirements, FPGA design and verification elements are managed in documents and spreadsheets external to DOORS. System engineers, project and program managers use DOORS, but most FPGA designers and verification engineers do not use DOORS. Although traceability between different requirement levels can be easily managed with any Requirements Management tool such as IBM Rational DOORS, there is a gap between requirements and other FPGA design elements.

During this webinar, we will present how Spec-TRACER™  solves this problem by providing direct integration with DOORS. We will also prove that automation of traceability helps you avoid errors with minimal effort to generate the traceability matrices required by customers for various functional safety standards.

Agenda: 

• Traceability in FPGA projects
• Traceability for Safety
• Traceability Automation
• Spec-TRACER™ with IBM® Rational® DOORS® demo
• Conclusion
• Q&A

Presenter Bio:

Janusz Kitel is a Requirements Management Specialist at Aldec, responsible for Spec-TRACER product. He has 5 years of experience in requirements engineering and over 10 years of experience in product quality assurance. Janusz received his M.S. in Electronics and Telecommunication from Silesian University of Technology and increased his knowledge about software engineering from complementary studies at AGH University of Science and Technology (Poland). His practical engineering experience includes areas in functional verification, DO-254 compliance and software development.