Essential Steps to Simplify VHDL Testbenches Using OSVVM  (EU)

Jim Lewis, VHDL Design and Verification Expert, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, February 15, 2024

3:00 PM - 4:00 PM (CET)


This “Getting Started” webinar focuses on the first, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing, self-checking tests, messaging, reports, and Open Source VHDL Verification Methodology (OSVVM) helper utilities.  

The “transaction” in transaction-based testing is just a fancy word for an abstraction that represents a single action on an interface – such as a Send or Get on a streaming interface. We will look at alternatives in implementing transactions – including using OSVVM’s Model Independent Transaction library. Using transactions is important because they accelerate test case development, increase reuse, and reduce maintenance costs.

Self-checking is essential in test cases as checking waveform output manually is time consuming, error prone, and soul-crushingly boring. Self-checking involves counting errors and using the count to create a pass/fail report when the test is completed. If we use signals (and there may be a collection, some of which might be in a different entity) we will need to sum them up and generate an error report. However, it is easy to forget one and give a false pass condition.  OSVVM simplifies error counting and makes it reliable by creating a data structure in a package and using it to track the multitude of error sources. The pass/fail report is created by looking at the entire data structure for errors – so nothing is missed. We can even track and report separate sources of errors – such as different interfaces.

Messaging (a.k.a. verbosity control) is about creating detailed informational messages when we are debugging and just pass/fail messages when running regressions. Since the messages may be generated by different entities, we need controls that have a wide scope. Furthermore, we may want to control different sources of messages independently. OSVVM simplifies the control of log messages (enable/disable) using the same data structure we use for tracking errors.

Test reports are about quickly finding which tests in a suite of tests failed and why. OSVVM creates two levels of test reports. The OSVVM build summary report gives a summary of the pass/fail status of each separate test case that was run, and the OSVVM test case report provides details on the self-checking, functional coverage, and scoreboard/FIFO usage for each test case. When running sets of tests (such as during regression testing), these reports help us quickly find which test cases failed and why.

The OSVVM helper utilities target simplifying testbench development with capabilities that include clock generation, reset generation and test case development with synchronization utilities such as WaitForClock and WaitForBarrier. 


OSVVM is a suite of libraries that allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex, randomized full chip or system level tests. OSVVM is developed by VHDL experts who actively contribute to VHDL standards development to provide VHDL with verification capabilities that rival SystemVerilog + UVM.

Getting your entire team united in using OSVVM will simplify deploying VHDL engineers to projects. Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study, in the FPGA market, 66% use VHDL for design, 58% use VHDL for verification, and 28% use OSVVM. Hence, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification.   

Webinar Duration
  • 45 min presentation/live demo
  • 10 min Q&A


Presenter Bio:

Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification.

Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and spacecraft. 

Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Jim brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.


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