Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces.
In the concluding part of this webinar series, we are now ready to apply advanced verification to a complex DUT. From a verification point of view, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately, there is very little awareness about the high risk this represents – not to mention all the late fixes required or, even worse, the escape of bugs into the customers’ products.
In this webinar, we will explain some typical problem scenarios, how they are handled in most projects, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally, we will show how such a testbench could be made using UVVM, and how this significantly improves overview, readability, maintainability, extensibility, debuggability, and reuse.
- Error prone corner cases for any communication interface
- Challenges when verifying a high number of interfaces
- Challenges when verifying simultaneously active interfaces
- Connecting higher level protocols with no physical interface to the DUT
- The structure of an advanced testbench
- Comprehensive functional coverage
- UVVM for advanced verification
- Solving the above using UVVM and VHDL Verification Components (VVCs)
- 45 min presentation/live demo
- 15 min Q&A