Enhancing the Simulation Testbench for VHDL-based FPGA Designs Part 3: Advanced Testbench for a Complex DUT (EU)

LIVE WEBINAR:

Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series)

Part 3: Advanced Testbench for a Complex DUT (EU)

Espen Tallaksen, CEO of EmLogic

Thursday, August 31, 2023

3:00 PM - 4:00 PM (CEST)

Abstract:

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces.

In the concluding part of this webinar series, we are now ready to apply advanced verification to a complex DUT. From a verification point of view, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately, there is very little awareness about the high risk this represents – not to mention all the late fixes required or, even worse, the escape of bugs into the customers’ products.

In this webinar, we will explain some typical problem scenarios, how they are handled in most projects, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally, we will show how such a testbench could be made using UVVM, and how this significantly improves overview, readability, maintainability, extensibility, debuggability, and reuse.

Agenda:

Error prone corner cases for any communication interface
Challenges when verifying a high number of interfaces
Challenges when verifying simultaneously active interfaces
Connecting higher level protocols with no physical interface to the DUT
The structure of an advanced testbench
Comprehensive functional coverage
Scoreboards
UVVM for advanced verification
Solving the above using UVVM and VHDL Verification Components (VVCs)
Q&A

Webinar Duration

45 min presentation/live demo
15 min Q&A

Presenter Bio:

Simon Southwell has 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development.

Espen Tallaksen, CEO of EmLogic

Espen is also the author and architect of UVVM and founder of previous Bitvis.

He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.