Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces.
In part 2 of this webinar series, we will show you how to verify a relatively simple DUT with high quality requirements using an advanced testbench without using any verification framework. We will also discuss the elements of an advanced testbench infrastructure to verify our simple DUT more efficiently, check and prove that we have indeed verified our simple DUT more thoroughly, start to use advanced Bus Functional Models (BFMs) that allow simpler and more advanced interface control, and introduce functional coverage.
Having shown you these more advanced testbench techniques, we will continue to show how UVVM can be used to implement them in the simplest ways possible and with a focus on readability, maintainability, and extensibility.
- What is required when verifying for higher quality?
- The elements of an advanced testbench infrastructure
- Advanced BFMs
- BFM vs Protocol Checkers
- BFM limitations
- Advanced randomization
- Specification Coverage, aka Requirements Coverage
- Introducing functional coverage
- UVVM advanced BFMs
- UVVM for high quality verification
- 45 min presentation/live demo
- 15 min Q&A