LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

Part 4: Advances in OSVVM's Verification Data Structures (EU)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, June 23, 2022

3:00 PM - 4:00 PM (CEST)


OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series.

This webinar focuses on advances in OSVVM data structures. OSVVM's Functional Coverage, Scoreboard, FIFO, and Memory data structures are now all based on singletons – in a similar fashion to what is done in AlertLogPkg.  

Using singletons significantly simplifies each data structure's USER API – the call interface. Specifically, users no longer need to use shared variables, protected types, and their complications. We will discuss the new APIs, their advantages, and some of the improvements OSVVM was able to make by using these.

Don't worry though, we still support the older protected type data structures. 

One of the advantages of the updated data structures was discussed in Part 3 of this webinar series – reports for Functional Coverage and Scoreboards are automatically generated simply by running the tests with OSVVM scripting and calling "EndOfTestReports" rather than "ReportAlerts" at the end of the test.

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC.
OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that:
  • Are simple to use and work like built-in language features.
  • Maximize reuse and reduce project schedule.
  • Improve readability and reviewability by the whole team including software and system engineers.
  • Facilitate debug with HTML based test suite and test case reporting.
  • Support continuous integration (CI/CD) with JUnit XML test suite reporting.
  • Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering.
  • Rival the verification capabilities of SystemVerilog + UVM.
OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification.   World-wide, 18% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey.   
Pre-Webinar Homework
Want to try out OSVVM before the webinar? See our OSVVM Script User Guide to run our demos. See:
If you prefer pdf (it has section numbers) see:

Webinar Duration: 

  • 50 min presentation/live demo 
  • 10 min Q&A


Presenter Bio:

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Jim Lewis is an innovator and leader in the VHDL community.   He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group.  He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology.  He is an expert VHDL trainer for SynthWorks Design Inc.   In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.  


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