Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their "Lite" or "Easy" approach.
Creating a verification component (VC) using OSVVM is simple enough that neither a "Lite" version nor a script is needed. This presentation is a walk through the steps to write a verification component that effectively utilizes OSVVM capabilities.
One big time saver in creating OSVVM's VCs is our Model Independent Transactions (MIT). MIT evolved from the observation that many interfaces do the same sort of transactions. For example, Address Bus Interfaces, such as AXI4, Avalon, and Wishbone, all do read and write operations. Similarly, streaming interfaces, such as AxiStream and UARTs, all do send and get operations. OSVVM defines a pattern, or if you prefer an internal standard, for the Address Bus transaction interface and transaction API. It does the same for Stream Interfaces.
The result of using OSVVM's MIT is that a VC developer can focus on writing the VC behavior. This makes OSVVM's VC based approach as simple as a "Lite" approach that codes interface behavior in a subprogram. Starting with a VC allows us to include additional capability – such as protocol and timing checkers. VCs also provide a path to greater capability – such as with an AXI4 interface where the Address Write, Write Data, Write Response, Address Read, and Read Data aspects of the interface are independent of each other and need to be handled by separate processes. With a VC, these capabilities can be incrementally added during the test process.
At the end of the day, OSVVM does not need a "Lite" version because we make writing verification components as simple as writing a procedure. Nothing more than a template is needed. Any of OSVVM's growing library of verification components can be used as a template.
OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC.
OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that:
- Are simple to use and work like built-in language features.
- Maximize reuse and reduce project schedule.
- Improve readability and reviewability by the whole team including software and system engineers.
- Facilitate debug with HTML based test suite and test case reporting.
- Support continuous integration (CI/CD) with JUnit XML test suite reporting.
- Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering.
- Rival the verification capabilities of SystemVerilog + UVM.
OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM . In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey.
- 50 min presentation/live demo
- 10 min Q&A