LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)
Part 1: OSVVM - Leading-Edge Verification for the VHDL Community (US)
Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, May 26, 2022
11:00 AM - 12:00 PM (PDT)
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Abstract:
OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA verification projects from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either simple or complex FPGA blocks.
Looking to improve your VHDL FPGA verification methodology? OSVVM is the right solution. We have all the pieces needed for verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them.
This webinar provides a broad overview of OSVVM's capabilities. You will learn the OSVVM way of:
- Creating a well-structured, testbench framework
- Creating verification components (overview – in Part 2 we will cover details)
- Creating test cases
- Using AffirmIf for self-checking
- Using logs for conditional message printing to facilitate debug
- Adding constrained random to your tests
- Using scoreboards for self-checking
- Adding functional coverage
- Using Intelligent Coverage Randomization – randomization using a functional
- coverage model.
- Using Alert to add protocol checks
- Test Synchronization and Watchdogs
- Test Wide Reporting
- Using OSVVM's Simulator Independent Scripting (overview – in Part 3 we will cover details)
- Creating Test Reports in HTML for Humans
- Creating Test Reports in JUnit XML for Continuous Integration
OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that:
- Are simple to use and work like built-in language features.
- Maximize reuse and reduce project schedule.
- Improve readability and reviewability by the whole team including software and system engineers.
- Facilitate debug with HTML based test suite and test case reporting.
- Support continuous integration (CI/CD) with JUnit XML test suite reporting.
- Provide buzz word features including Constrained Random, Functional
- Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering.
- Rival the verification capabilities of SystemVerilog + UVM.
Webinar Duration:
- 50 min presentation/live demo
- 10 min Q&A
Presenter Bio:
Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
