Better FPGA Verification with VHDL (Four Part Webinar Series)
Part 1: OSVVM - Leading Edge Verification for the VHDL Community
Part 2: Faster than "Lite" Verification Component Development with OSVVM
Part 3: OSVVM's Test Reports and Simulator Independent Scripting
Part 4: Advances in OSVVM's Verification Data Structures
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Part 1: Leading Edge Verification for the VHDL Community
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, May 26, 2022
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Part 2: Faster than "Lite" Verification Component Development with OSVVM
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, June 9, 2022
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Part 3: OSVVM's Test Reports and Simulator Independent Scripting
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, June 16, 2022
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Part 4: Advances in OSVVM's Verification Data Structures
Presenter: Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair
Thursday, June 23, 2022
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Bio:
Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
