LIVE WEBINAR: Automating UVM flow using Riviera-PRO’s UVM Generator (US)
Sunil Sahoo, Corporate Applications Engineer at Aldec
Thursday, February 24, 2022
11:00 AM - 12:00 PM (PST)
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Abstract:
UVM is a versatile verification methodology that enables users to run advanced verification flows for large scale FPGAs and SoC FPGAs. However, because of its advanced nature, writing UVM from scratch can be a complex and tedious task. Riviera-PRO’s new UVM Generator feature alleviates some of the complexity by automatically creating the UVM testbench for any given design under test written in VHDL or Verilog. It also creates a basic framework of the UVM environment with all its components. Along with SystemVerilog source files, the UVM Generator automatically creates the TCL macros for controlling the simulation process. This webinar focuses on how to use UVM Generator and the benefits it brings to users creating UVM code from scratch.
The UVM Generator creates the following components as part of the UVM testbench: Test, Virtual Sequences, Environment, Environment Configuration, Predictors, Scoreboards, Agents, Agent Configuration, Driver, Monitor, Coverage, SV interface, Sequence Items and Sequences. The generated UVM code can also be displayed in Riviera-PRO’s UVM Graph Window.
Agenda:
- Introduction to the UVM Generator
- Components of UVM testbench
- Generated Scripts
- Live demo
- Conclusion
- Q&A
Webinar Duration:
- 45 min presentation/live demo
- 15 min Q&A
Presenter Bio:
Sunil Sahoo provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions that include Digital Design Engineer Verification Engineer and Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.
