The ALINT-PRO Static Design Verification solution includes DO-254 HDL Ruleset targeted for safety critical designs that require DO-254 compliance. Recently, this DO-254 Ruleset was enhanced with more than 80 new rules, adding a significant amount of code checks for Verilog and VHDL-based designs relevant to coding practices, clock domain crossings, safe synthesis, and code reviews.
This webinar will provide an overview of the newly added DO-254 rules, from their specification to implementation and code examples. We will also discuss the available tool qualification data package for ALINT-PRO.
- New DO-254 coding rules for VHDL and Verilog
- Rule examples
- Coding Practices
- Clock Domain Crossings
- Safe Synthesis
- Code Reviews
- Tool Qualification Data Package
- Q & A