In this third webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL's RTL coding capabilities.
For a long time, VHDL was more verbose than other languages, however, much of that was fixed with VHDL2008. At the completion of VHDL-2008, VHDL was as concise as Verilog/SystemVerilog. VHDL-2019 continues working to make VHDL more concise and expressive.
Two big RTL enhancements VHDL-2019 added are VHDL Interfaces and conditional compilation. This was covered in the Part 1, “VHDL-2019 Interfaces, Conditional Analysis, File IO, and The New Environment.”
This presentation furthers the discussion of RTL enhancements and covers the following:
- Optional trailing semicolon at the end of interface list
- All interface lists are ordered
- Allow functions to know the output vector size
- Inferring signal and variable constraints from initial values
- Conditional expressions in object declarations
- Conditional return
- Component declaration syntax regularization
VHDL-2019 was requested by users, ranked by users, scrutinized by users, written by users, and balloted by the VHDL community. As such, it should be clear to the vendor (simulation and synthesis) community that the users want these features.
Through its revisions, 1987, 1993, 2002, 2008, and now 2019, VHDL has evolved to be capable design and verification language.
Aldec started their implementation of VHDL-2019 prior to the standard being completed and is well into their implementation. If your vendor cannot tell you definitively if and when they will support the new features you want to use on your VHDL projects, then maybe it is time to find a vendor who will.
What about Verilog and SystemVerilog? Despite overwhelming marketing for SystemVerilog, it is clear from the Wilson Verification Survey, that VHDL is the preferred FPGA design and verification language. For many applications, FPGA is the future. Just like in the software world, FLASH is usually preferred over ROM.
The VHDL standards committee work is never done. It takes a collaboration of people with different skills to successfully update the standard. Some of these members are language experts, some design experts, and some verification experts. Join us in writing the next revision. See: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome.
The presenter, Jim Lewis, is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
Whether teaching, developing OSVVM, doing consulting VHDL development, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
- 50 min presentation/live demo
- 10 min Q&A