LIVE WEBINAR: cocotb: Use Python and bring joy back to verification (US)

Presenter: Philipp Wagner, co-maintainer of cocotb and Hardware/Software Engineer at lowRISC

Thursday, June 4, 2020

11:00 AM – 12:00 PM PDT

Abstract: 

cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. cocotb encourages the same philosophy of design re-use and randomized testing as UVM, however is implemented in Python rather than SystemVerilog. With cocotb, VHDL/Verilog/SystemVerilog are normally only used for the design itself, not the testbench.

In this webinar we will introduce cocotb and show how to get started with a small design using Aldec’s Riviera-PRO. We will also show a more complex example, giving you a taste how cocotb could add value -- and joy! -- to your next verification project.

Agenda: 

• Overview of cocotb
• Getting started with Riviera-PRO
• Complex examples with cocotb
• Q&A

Presenter Bio:

Philipp Wagner is co-maintainer of cocotb and Hardware/Software Engineer at lowRISC in Cambridge, UK, where he is involved in OpenTitan, the first Open Source Root of Trust chip. For many years Philipp has been working on the intersection of digital hardware, software and open source. He is passionate about developer productivity, communities, and bridging the gap between hardware and software development methodologies. Philipp is Founding Director of the Free and Open Source Silicon Foundation, and has received a M.Sc. and PhD (Dr.-Ing.) degree in Electrical Engineering from Technical University Munich, Germany.