LIVE WEBINAR: Designing Finite State Machines for Safety Critical Systems (US)

Presenter: Alexander Gnusin, Design Verification Technologist

Thursday, April 16, 2020

11:00 AM – 12:00 PM PDT

Abstract: 

Finite State Machines (FSM) are a  key part of safety-critical design control logic. During the operation of the FPGAs within the systems, single-event upsets or other radiation effects can cause the internal logic to flip to an incorrect value from ‘0’ to ‘1’ or ‘1’ to ‘0’ in a non-deterministic way, causing the system to fail.  As transistors shrink, errors are becoming much more common; in a modern chip the devices are so small that cosmic rays or alpha particles can change the value of bits that are stored in FSM registers. 

In this webinar we will provide the various methods on how to develop robust and safe FSMs - from best practices in FSM design to highly reliable FSM design methods , allowing designers to develop state machines with transient errors detection and correction.

Agenda: 

• Best Practices in FSM Designs
• Error correction for FSM design
• Conclusion
• Q&A

Presenter Bio:

Alexander Gnusin is Verification Methodology specialist art Aldec. Currently, he is responsible for ALINT-PRO product improvements. Alexander Gnusin has 23 years of hands-on Design and Verification experience, gained in well-known design houses - Motorola Semiconductors, IBM, Nortel Networks, Ericsson. As Verification Prime for multi-million gates project, he combined various verification methods - LINT, Formal Property checking, dynamic simulation, hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of technology.