Due to the size and complexity of current hardware designs, the design verification task has become increasingly complex and lengthy. Today, the goal is to clean up the design code as much as possible prior to entering the design verification stage. Such design code cleanup, performed during relatively short time, may significantly reduce overall design verification time and effort. As Systemverilog design constructs gain popularity among hardware designers, it is increasingly important to assist designers with Systemverilog design code verification and cleanup.
ALINT-PRO™ is a design verification solution for Systemverilog, Verilog and VHDL RTL that is able to statically verify and cleanup the code far beyond compiler-level checks. It is capable of statically verifying most of the popular Systemverilog design constructs, uncovering some of the critical design issues early in the design cycle.
- Design Verification Challenge: The Overview
- Problem: Low quality Systemverilog design code for Design Verification
- Solution: Static Code Verification prior to Dynamic one
- ALINT-PRO Systemverilog code checks: The overview
- ALINT-PRO place in overall Design Verification process
- ALINT-PRO Systemverilog Plugin Live demo