1. Which FPGA technologies do you target? (Check all that apply)*
2. If you target AMD-Xilinx FPGAs, which device families do you target? (Check all that apply)*
3. If you target Intel FPGAs, which device families do you target? (Check all that apply)*
4. If you target Microchip FPGAs, which device families do you target? (Check all that apply)*
5. What are your target markets and applications? (Check all that apply)*
6. Which safety-critical development standards are you required to meet? (Check all that apply)*
7. How many FPGA design engineers are in your team?*
8. How many FPGA verification engineers are in your team?*
9. What is your target design language? (Check all that apply)*
10. What is your target verification language? (Check all that apply)*
11. Do you use VHDL 2019 with your current projects?*
12. Which standard verification framework or methodology do you use? (Check all that apply)*
13. If you use a home-grown verification framework, please describe how you generate stimulus, manage simulations/regressions and collect test results and coverage.
14. Which verification techniques do you use? (Check all that apply)*
15. Proportionally, how much project time do you spend between FPGA simulation and testing?*
16. How much time does it take to complete a full FPGA system simulation?*
17. Which high-speed interfaces do you need to simulate? (Check all that apply)*
18. How many asynchronous clock domains do you have on a given FPGA project?*
19. How many soft CPU cores do you implement within the FPGA?*
20. How many hard CPU cores do you use within the FPGA?*
21. Do you use any commercial verification IPs (VIPs)?*
22. Which development frameworks, virtualizers or emulators do you use for modeling physical hardware? (Check all that apply)*
23. Do you need to have the development framework integrated with the HDL simulator?*
24. Do you need to have the development framework or HDL simulator integrated with the FPGA board (hardware in the loop)?*
25. Which type of physical FPGA boards do you use for prototyping your design? (Check all that apply)*
26. Do you need a multi-threaded parallel HDL simulator?*
27. Do you need a formal verification solution?*
28. Do you need a cloud-based HDL simulation tool?*
29. Do you need a mixed-signal simulation solution?*
30. Please use this section to provide additional feedback regarding feature requests, 3rd party integrations, verification challenges, new use cases or recommendations for Aldec. Thank you for your time! We look forward to your feedback.