1. Which FPGA technologies do you target? (Check all that apply)
*
Achronix
AMD-Xilinx
Efinix
Gowin
Intel
Lattice
Microchip
Quicklogic
Other
2. If you target AMD-Xilinx FPGAs, which device families do you target? (Check all that apply)
*
Versal ACAP
Zynq UltraSCALE+RFSoC
Zynq UltraSCALE MPSoC
Zynq-7000 SoC
Virtex UltraSCALE+
Virtex UltraSCALE
Kintex UltraSCALE+
Kintex UltraSCALE
Artix UltraSCALE+
Virtex 7
Artix 7
Kintex 7
Spartan 7
Spartan 6
We do not target AMD-Xilinx FPGAs
3. If you target Intel FPGAs, which device families do you target? (Check all that apply)
*
Agilex SoC
Stratix 10
Stratix V
Stratix III or older
Arria 10
Arria V
Arria II or older
Max 10
Max V
Max II or older
Cyclone 10
Cyclone V
Cyclone IV
Cyclone III or older
We do not target Intel FPGAs
4. If you target Microchip FPGAs, which device families do you target? (Check all that apply)
*
PolarFire SoC
PolarFire
SmartFusion SoC
SmartFusion
IGLOO and IGLOO 2
ProASIC 3
RT PolarFire
RTG4
RTAX
RT ProASIC 3
RTSX-SU
We do not target Microchip FPGAs
5. What are your target markets and applications? (Check all that apply)
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Automotive
Avionics
Consumer Applications
High Performance Computing
High Frequency Trading
Image and Video Processing
Industrial and Robotics
Medical
Military and Defense
Nuclear
Railways
Space
Other
If you selected 'Other' please provide details
6. Which safety-critical development standards are you required to meet? (Check all that apply)
*
DO-254
ISO-26262
IEC-61508
MIL-STD-882
IEC-61513
IEC-60601
EN-50129
IEC-61511
We do not work on safety-critical projects
7. How many FPGA design engineers are in your team?
*
1
2
3-5
6-10
11 or more
8. How many FPGA verification engineers are in your team?
*
0
1
2
3-5
6 or more
9. What is your target design language? (Check all that apply)
*
VHDL
Verilog
C
Other
If you selected 'Other' please provide details
10. What is your target verification language? (Check all that apply)
*
VHDL
Verilog
SystemVerilog
SystemC
C/C++
Python
Other
If you selected 'Other' please provide details
11. Do you use VHDL 2019 with your current projects?
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Yes
No, but we plan to in the next 1-2 years
No, but we plan to in the next 3-4 years
No, and we can't foresee a need to
12. Which standard verification framework or methodology do you use? (Check all that apply)
*
OSVVM
UVVM
UVM
Cocotb
C/C++/SystemC TLM
We do not use any of these verification frameworks
We plan to start using a verification framework in the next year
We use our home-grown verification framework
13. If you use a home-grown verification framework, please describe how you generate stimulus, manage simulations/regressions and collect test results and coverage.
14. Which verification techniques do you use? (Check all that apply)
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Directed Tests
Code Coverage
Functional Coverage
Assertions
Constrained-Random
Transaction-Based Verification
Linting
CDC Analysis
15. Proportionally, how much project time do you spend between FPGA simulation and testing?
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10% in simulation and 90% in testing
30% in simulation and 70% in testing
50% in simulation and 50% in testing
70% in simulation and 30% in testing
90% in simulation and 10% in testing
16. How much time does it take to complete a full FPGA system simulation?
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Less than 1 hour
1 hour to 8 hours
8 hours to 1 day
1 day to 5 days
6 days or more
17. Which high-speed interfaces do you need to simulate? (Check all that apply)
*
PCIe
Ethernet
SATA
USB
DisplayPort
HDMI
DDR
MIPI CSI
MIPI DSI
NVMe
HBM
None
Other
If you selected 'Other' please provide details
18. How many asynchronous clock domains do you have on a given FPGA project?
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2-5
6-10
11 or more
We have a fully synchronous design
19. How many soft CPU cores do you implement within the FPGA?
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0
1
2
3
4
5 or more
20. How many hard CPU cores do you use within the FPGA?
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0
1
2
3
4
5 or more
21. Do you use any commercial verification IPs (VIPs)?
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Yes
No
22. Which development frameworks, virtualizers or emulators do you use for modeling physical hardware? (Check all that apply)
*
Matlab/Simulink
QEMU
Renode
GNU Radio
GNU Octave
Python-based framework
We do not use such development framework
Other
If you selected 'Other' please provide details
23. Do you need to have the development framework integrated with the HDL simulator?
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No
Yes
24. Do you need to have the development framework or HDL simulator integrated with the FPGA board (hardware in the loop)?
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No
Yes
25. Which type of physical FPGA boards do you use for prototyping your design? (Check all that apply)
*
Homegrown prototyping FPGA boards
FPGA boards from the FPGA chip vendors
FPGA boards from commercial FPGA board vendors
Custom system/target boards with the FPGA
26. Do you need a multi-threaded parallel HDL simulator?
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No, we already have one
Yes, we will need one within the next 3 years
Yes, but not for at least 3 years
No, and can't imagine we will
27. Do you need a formal verification solution?
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No, we already have one
Yes, we will need one within the next 3 years
Yes, but not for at least 3 years
No, and can't imagine we will
28. Do you need a cloud-based HDL simulation tool?
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No, we already have one
Yes, we will need one within the next 3 years
Yes, but not for at least 3 years
No, and can't imagine we will
29. Do you need a mixed-signal simulation solution?
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No, we already have one
Yes, we will need one within the next 3 years
Yes, but not for at least 3 years
No, and can't imagine we will
30. Please use this section to provide additional feedback regarding feature requests, 3rd party integrations, verification challenges, new use cases or recommendations for Aldec. Thank you for your time! We look forward to your feedback.
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