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BEGIN:VEVENT
DTSTAMP:20260414T081737Z
DTSTART:20220616T130000Z
DTEND:20220616T140000Z
SUMMARY:Better FPGA Verification with VHDL: Part 3 - OSVVM's Test Reports and Simulator Independent Scripting (EU)
DESCRIPTION:Better FPGA Verification with VHDL: Part 3 - OSVVM's Test Reports and Simulator Independent Scripting (EU)\n\n
UID:AO_EVENT_23474_00c8__1652181300060
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