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BEGIN:VEVENT
DTSTAMP:20260530T162238Z
DTSTART:20220526T180000Z
DTEND:20220526T190000Z
SUMMARY:Better FPGA Verification with VHDL: Part 1 OSVVM - Leading-Edge Verification for the VHDL Community (US)
DESCRIPTION:Better FPGA Verification with VHDL: Part 1 OSVVM - Leading-Edge Verification for the VHDL Community (US)\n\n
UID:AO_EVENT_23474_00c5__1652180502056
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